(1) Field of the Invention
This invention relates generally to voltage regulators, and more particularly to a current mode low dropout (LDO) voltage regulator having a linear adaptive biasing current technique.
(2) Description of the prior Art
Low-dropout (LDO) linear regulators are commonly used to provide power to low-voltage digital circuits, where point-of-load regulation is important. In these applications, it is common for the digital circuit to have different modes of operation. As the digital circuit switches from one mode of operation to another, the load demand on the LDO can change quickly. This quick change of load results in a temporary glitch of the LDO output voltage. Most digital circuits do not react favorably to large voltage transients. An important goal for voltage regulators is to isolate sensitive circuitry from the transient voltage changes of the battery.
Conventional LDO regulators are very problematic in the area of transient response. The transient response is the maximum allowable output variation for a load current step change and must be frequency compensated in order to ensure a stable output voltage. Conventional means to compensate frequency dependencies are limiting the load regulation performance and the accuracy of the output.
Linear voltage regulators (LDO's) have either a fixed biasing current, which results in poor efficiency for small load currents, or they have a (nonlinear) dynamic biasing current, which changes the internal operating point when the load varies. This negatively affects stability and requires a large silicon area for compensation. Further the LDO suffers in one or the other way because of these variations.
LDOs generally should consume little standby current and silicon area. Depending on the application they must achieve good performance values in terms of power supply rejection (PSSR), transient response to load current changes, and DC regulation accuracy. Conventional LDOs require a large capacitor for “Miller compensation” to stabilize the regulator feedback loop under all operating conditions.
There are patents known dealing with these problems as PSSR, transient response to load current changes and regulation accuracy:
U.S. Pat. No. (6,703,813 to Vladislav et al.) describes an LDO regulator arranged to provide regulation with a pass device, a cascode device, a level shifter, an error amplifier, and a tracking voltage divider. The error amplifier is arranged to sense the output voltage and provide an error signal to the pass device via the level shifter. The level shifter changes the DC level of the error signal such that the pass device is isolated from damaging voltages. The cascode device is arranged to increase the impedance between the output node and the pass transistor such that the LDO regulator can sustain input voltages that exceed process limits without damage. The cascode device is biased by the tracking voltage divider. The tracking voltage divider adjusts the biasing to the cascode device such that a decreased input voltages result in lower impedance, and increased input voltages result in higher impedance.
U.S. Pat. No. (6,046,577 to Rincon-Mora et al.) discloses an improved low-dropout (“LDO”) voltage regulator incorporating a transient response boost circuit which is added to the slew-rate limited node at the control terminal of the LDO voltage regulator output transistor and providing improved transient response performance to the application of various load current step stimuli while requiring no standby or quiescent current during zero output current load conditions. The transient boost circuit supplies current to the slew-rate limited node only upon demand and may be constructed as either a localized positive feedback loop or a number of switching devices, which conduct current only during slew-rate conditions.
U.S. Pat. No. (6,518,737 to Stanescu et al.) discloses a low dropout voltage regulator with non-Miller frequency compensation. The LDO circuit has two wide-band, low-power cascaded operational transconductance amplifiers (OTAs): an error amplifier and a unity-gain-configured voltage follower. The unity-gain-configured voltage follower drives a gate of a power PMOS path transistor with a high parasitic gate capacitance. The wide-band, low-power OTAs enable the use of a single, low-value load capacitor with a low equivalent series resistance (ESR). A frequency compensation capacitor is connected in parallel with the upper resistor of a feedback network, which introduces a zero-pole pair that enhances the phase margin close to unity-loop-gain frequency.
Furthermore Gabriel Rincon-Mora describes “A low-Voltage, Low-quiescent Current LDO Regulator” in IEEE Journal of Solid States Circuits, Vol 33, no 1, January 1998 and Marc G. Degrauwe et al. describe “Adaptive Biasing CMOS Amplifiers!” in IEEE Journal of Solid States Circuits” Vol. 17, no. 3, June 1982.